A UVM Verification Component (UVC) is a packaged, reusable verification building block in the UVM ecosystem. UVCs encapsulate the complete verification environment logic for a specific protocol or interface, including stimulus generation, driver, monitor, scoreboarding, and coverage collectors. They enable rapid testbench assembly and consistent verification across projects.
UVCs are like plug-and-play blocks, which are useful to verify standard protocols like AHB or AXI in your design, rather than writing your own tests to verify this. It can also be used to verify a larger block, like a SoC or a Subsystem, in which an IP is already verified (IP UVC is used here).
Types of UVCs
There are two types of UVCs: Interface UVCs and Module UVCs.
Interface UVCs
- Bus based UVCs. For example: AMBA AHB, AXI, Ethernet etc.
- These types of UVCs are specific to a protocol and can be reused everywhere the protocol is used.
- Connected to DUT using an interface
- Contains Sequencer, Driver and Monitor inside the UVC
- These UVCs generate stimulus and send it to DUT via interface
- In the testbench diagram below, AHB UVC is an interface UVC
Module UVCs
- Module UVCs are based on particular flavour of design. Eg. Scoreboard, Register model etc.
- Reusable everywhwhere the DUT is used.
- In the testbench diagram below, Scoreboard is a Module UVC
No responses yet