In System Verilog Assertion (SVA), it is possible to check clock frequencies.
Below code represents a simple assertion to check clk1 is 100Mhz.
//SVA to check clk1 is 100Mhz
property clk_period;
time curr_time;
@(posedge clk1)
(1, curr_time = $time) ##1 (($time - curr_time) == 10ns);
endproperty
check1_clk1_100mhz: assert property(clk_period);Now, the above assertion is good but if you want to run this assertion on multiple clocks, it makes more sense to make it generic i.e. with user defined inputs. So now, we will also add a tolerance limit so that this assertion can be run in GLS simulation as well. Why tolerance? because in reality, no clock is pure 100Mhz, it can be 99.999Mhz or can also be 100.001Mhz, so a tolerance value is defined by the designers which state the clock should stay between a {minimum to maxmimum} range of period.
//Generic SVA to check clock period
property clk_period(logic clk, time timeperiod, tolerance);
time curr_time;
(1, curr_time = $time) ##1 (($time - curr_time >= (time_period - tolerance)) &&
($time - curr_time <= (time_period + tolerance)));
endproperty
//Check1 to check clock "clk1" has frequencey of 100Mhz with tolerance of +-1ns
check1_clock_100mhz: assert property(clk1, 10ns, 1ns);
//Check2 to check clock "clk_pp" has frequencey of 500Mhz with tolerance of +-3ns
check2_clock_500mhz: assert property(clk_pp, 2ns, 3ns);
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