About us
The Techie Blog — your trusted guide to mastering functional verification, UVM, and advanced digital design concepts.
We’re on a mission to make hardware verification education simple, structured, and practical for:
🧠Aspiring verification engineers
🛠️ Working professionals upskilling in UVM/SystemVerilog
🎓 Students preparing for VLSI roles and internships
A few things we’re great at
Functional verification is not just about learning UVM or System Verilog. It takes much more than these two skills.
UVM
This course teaches the basics of UVM along with projects to help understand better and test your skills.
Power Aware Verification
Power Aware Verification uses UPF as input to verify behaviour of your RTL design.
System Verilog
System Verilog is Hardware Description Language (HDL) which is widely used for Design and Verification.
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Explore Our Blog
What is Metric Driven Verification (MDV)?
Metric Driven Verification (MDV) is a methodology in which the verification process is guided and measured by[…]
Different types of coverage in Metric Driven Verification (MDV)
Metric Driven Verification (MDV) depends heavily on different types of coverages to quantify and close verification progress.[…]
Difference between uvm_config_db and uvm_resource_db?
What is uvm_config_db? uvm_config_db is a high-level, user-friendly mechanism used in UVM to pass configuration objects or[…]