UVM VERIFICATION

Before deep diving into UVM, these are the prerequisites.

What is Functional Verification

SYSTEM VERILOG ESSENTIALS FOR UVM

• SystemVerilog classes and OOP
• Interfaces, Modports, and Clocking Blocks
• Constraints and Randomization
• Functional coverage
• Inheritance and Polymorphism
• Virtual interfaces
• TLM basics

UVM Overview and Architecture

1. Introduction to UVM
2. What is Metric Driven Verification
3. What is UVM Verification Component (uVC)
4. How Interface UVC works?

COVERAGE

Different types of coverage in Metric Driven Verification (MDV)

UVM Testbench1: D Flip Flop

UVM QUESTIONS

What is the difference between uvm_config_db and uvm_resource_db?
What is Type Safety in UVM?

SYSTEM VERILOG ASSERTIONS (SVA) QUESTIONS

SVA to check clock frequency