About us
The Techie Blog — your trusted guide to mastering functional verification, UVM, and advanced digital design concepts.
We’re on a mission to make hardware verification education simple, structured, and practical for:
🧠Aspiring verification engineers
🛠️ Working professionals upskilling in UVM/SystemVerilog
🎓 Students preparing for VLSI roles and internships
A few things we’re great at
Functional verification is not just about learning UVM or System Verilog. It takes much more than these two skills.
UVM
This course teaches the basics of UVM along with projects to help understand better and test your skills.
Power Aware Verification
Power Aware Verification uses UPF as input to verify behaviour of your RTL design.
System Verilog
System Verilog is Hardware Description Language (HDL) which is widely used for Design and Verification.
Version control tools
Master Git & SVN — the essential tools behind collaborative chip design. Learn Git and SVN the right way — tailored for hardware and verification engineers.
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Explore Our Blog
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Before reading how an Interface UVC works, you should know what is a UVC and types of[…]
SVA to check clock frequency
In System Verilog Assertion (SVA), it is possible to check clock frequencies. Below code represents a simple[…]
What is Git?
Git is a distributed version control system created by Linus Torvalds. It is fast, scalable, and ideal[…]