Before reading how an Interface UVC works, you should know what is a UVC and types of UVC. You can go through this post What is UVM Verification Component (uVC) to revise the basics first.
Now, as we already know the difference between Interface and Module UVC, the next question is how the Interface UVC architecture looks like? Below diagram shows a very basic architecture of an Interface UVC and how different components interacts with each other and their roles.
SEQUENCE:
A sequence generates packets (transaction object) which include information like address, data etc. Example:
class my_sequence extends uvm_sequence#(my_transaction);
...
task body();
my_transaction tr = my_transaction::type_id::create("tr");
tr.addr = 0x12341234;
tr.data = 0xabcdabcd;
......
......
start_item(tr);
finish_item(tr);
endclassSEQUENCER:
Sequencer sends transactions to the driver. Its gets the item from sequencer and sends it driver when requested. Example:
class my_sequencer extends uvm_sequencer(my_transaction);
`uvm_component_utils(my_sequencer)
//New function
.....
endclassDRIVER:
Driver gets the transaction packet from Sequencer using “get_next_item” and drives the values of the packet to DUT using the UVC specific “drive_to_dut” task. Example:
class my_driver extends uvm_driver#(my_transaction);
...
virtual task run_phase(uvm_phase phase);
forever begin
my_transaction tr;
seq_item_port.get_next_item(tr);
drive_to_dut(tr); // send signal-level activity
seq_item_port.item_done();
end
endtask
endclass
//Example drive_to_dut task
task drive_to_dut(my_transaction tr);
vif.addr < = tr.addr;
vif.data < = tr.data;
vif.write < = 1;
@(posedge vif.clk);
vif.write < = 0;
endtaskMONITOR:
Monitor observes everything. It tracks down the information being driven on the virtual interface, collects it and send it to the scoreboard/coverage blocks. Example:
class my_monitor extends uvm_monitor;
...
virtual task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
if (vif.valid) begin
my_transaction tr = my_transaction::type_id::create("tr");
tr.addr = vif.addr;
tr.data = vif.data;
analysis_port.write(tr); // send to scoreboard
end
end
endtask
endclass
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